Join us in this webinar to learn more about the SiFive USB 3.2 IP solution, including retimer, for high-speed consumer applications. We will review IP engineering features, operations, configurations, protocols and implementation guidelines in detail.
SiFive's USB 3.2 Gen2 retimer IP cores are compliant with the USB 3.2 Appendix E standard. SiFive USB 3.2 Gen 2 supports up to 10 Gbps of bandwidth, includes a USB 3.2 Gen2 single lane PCS layer and supports all low power states.
Who should attend?:
Consumer product chip designers, high-speed interface IP designers, IP application engineers, IP architects and system engineers.
Founder of IPnest and Analyst at SemiWiki
Sanket Apurvabhai Shah has over 9 years of experience in semiconductor industry, mainly in IP verification, environment development and Gate Level Simulation. At SiFive, Sanket has lead verification efforts in verifying USB 3.1 Gen1, Gen2 device controller, USB 3.2 retimer, WireleIss retimer and has been part of verifying AMBA protocols and FPGA emulation teams for USB 3.2 retimer. He has been a part of more than a dozen soft IP releases. Sanket holds bachelor’s degree in Electronics & Telecommunication from R.C. Patel Institute of Technology, North Maharashtra University, Jalgaon, Maharashtra, India. Visit the LinkedIn profile...
Director, SoC IP Product Marketing,
As the Director of SoC IP Product Marketing at SiFive, Ketan Mehta is responsible for Interlaken, Ethernet, HBM memory and other high-speed interfaces. With over 25 years of experience in engineering and product planning, Ketan has a rich background in IP connectivity solutions for various applications including networking, storage, data center and cloud. He received his M.S. degree in electrical engineering from The University of Texas at San Antonio, and his MBA from San Jose State University. Visit the LinkedIn profile...
Vikas Aravind Kulkarni is the Director of IP Engineering at SiFive where he oversees USB IPs. He has over 20 years of experience in semiconductor engineering. Prior to joining SiFive, Vikas was the director of engineering for IP development at Innovative Logic. He has also held management positions at Aftek, Rambus and GDA Technologies. Vikas earned his MTech degree at Mysore University. Visit the LinkedIn profile...
The SiFive Connect webinar series is designed to be highly educational and interactive, offering attendees a direct connection to industry experts. Each one-hour long webinar will take place twice on the same day – once at 9 a.m. PDT and again at 6 p.m. PDT enabling our global audience to choose the time that works best for them. If you are unable to attend either of the events, please register anyway and we will send you a link to the recording after the webinar.