Part I: RISC-V 101

 
This one-hour webinar took place on Sep 12, 2017 

This webinar provided an introduction to RISC-V, covering areas such as the Register File, Instruction Types, Modes, Interrupts, and Control and Status Registers. Prior knowledge of RISC-V is not necessary, but having a basic understanding of Computer Architecture would be beneficial.
 
Hosted by:
 
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Drew Barbier; Field Engineer at SiFive, Inc.
Drew has worked in the Semiconductor industry for over 10 years in various engineering and customer facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great. 
 
 
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Krste Asanovic, Chief Architect at SiFive, Inc. 
In addition to serving as Chief Architect at SiFive, Krste is a Professor in the EECS dept. at the U. of California, Berkeley, where he also serves as Director of the ASPIRE Lab. Krste leads the RISC-V ISA project at Berkeley, and is Chairman of the RISC-V Foundation. He is an ACM Distinguished Scientist and an IEEE Fellow. Krste Received a PhD from UC Berkeley and a BA from the U. of Cambridge. 
 
 
 
 Post Webinar Materials

 

 

Part II: Introduction to SiFive RISC-V Core IP

 
This one-hour webinar took place on Oct 17, 2017 
 
This webinar focused on Embedded Developers who are interested in learning more about the RISC-V architecture. 
Part two introduced the SiFive RISC-V Core IP Products; the E31 RISC-V Core IP and the E51 RISC-V Core IP.
 
 
Hosted by:
 
HOST2.jpg
 
Drew Barbier; Field Engineer at SiFive, Inc.
Drew has worked in the Semiconductor industry for over 10 years in various engineering and customer facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great. 
 
 
 
 
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Jack KangVP of Product and Business Development @Sifive, Inc.
Jack has held a variety of senior business development, management, and product marketing roles at both NVIDIA and Marvell, with a track record of successful, large scale design wins. Jack started his career as a frontend design engineer, focusing on CPU architecture and design. Jack received his BS degree in Electrical Eng. and Computer Science from UC Berkeley.

 

 

Post Webinar Materials

  

 

Part III: Evaluating SiFive RISC-V Core IP 

REGISTER HERE

This one-hour webinar will take place on December 11th, 2017. 
 
This webinar focused on Embedded Developers who are interested in learning more about the RISC-V architecture. 
Part two introduced the SiFive RISC-V Core IP Products; the E31 RISC-V Core IP and the E51 RISC-V Core IP.
 

Speaker info coming soon.

 

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