Ethernet has been used as a mainstream solution for chip-to-chip and die-to-die connectivity. In this webinar, we will review some of the key required features of Ethernet MAC/PCS from 800G down to 10G. We will address various types of Forward Error Correction engines (FEC) to improve the BER of the channel/links. We will analyze how the latest advances in packaging technology have allowed moving the ethernet functions from the main die to chiplets simplifying the system and improving the cost/power/performance of the overall solution.
Chip-to-Chip connectivity using Ethernet, improving link error rates and packaging technology
Who Should Attend?:
Designers, Architects, Marketing, Package engineers
Sr. Director, Product/Application Marketing, Interface IP
As the Sr. Director of Interface IP at OpenFive, Ketan Mehta is responsible for HBM Memory, Interlaken, Ethernet, Die-to-Die links, and other high-speed interfaces. With over 25 years of experience in engineering, product planning and marketing, Ketan has a rich background in IP connectivity solutions for various applications including high performance computing (HPC), AI, networking, data center, and storage. He received his M.S. degree in electrical engineering from The University of Texas at San Antonio, and his MBA from San Jose State University.
OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures.
With customizable and differentiated IP for Artificial Intelligence, Edge Computing, HPC, and Networking solutions, OpenFive develops domain-specific SoC architectures based on high-performance, highly-efficient, cost-optimized IP to deliver scalable, optimized, differentiated silicon.