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A Letter From the (New) CEO:
On August 15, we announced that regarded industry veteran Naveed Sherwani has joined SiFive as CEO. We invited him to share his vision for the company and his optimism for fomenting a revolution in the semiconductor industry.

Naveed headshot.jpgHello, SiFive Download readers! It’s great to e-meet you all. I am so honored and excited by the opportunity to join SiFive at such a pivotal time in the evolution of RISC-V. Over the past year, SiFive has achieved some significant milestones: we launched our Freedom SoC platforms, released our Coreplex IP, introduced a brand new IP licensing process and most recently, capped off a recent funding round that will make it possible for our organization to continue to drive innovation for the RISC-V community. But believe me when I tell you - we are just getting started.

When people ask me what attracted me to join SiFive, I tell them two things: Over the course of my 30-plus year career, I’ve been involved in the development of more than 300 chips. And never have I seen the potential for such a radical sea change in the industry. Second, there is no doubt in my mind that RISC-V will succeed - and no one is better positioned to take advantage of its success than SiFive.

The semiconductor industry needs to fundamentally change if it is to survive. We need to attract the best minds in technology to solve these thorny hardware challenges, and we need to enable innovation in every corner of the globe, not just four or five design centers. I’m excited to be on this journey together, and would love to hear from you. My inbox is always open - please drop me a line at, or introduce yourself at one of the many industry conferences SiFive will attend in the coming months.

-- Naveed

The (New) News Doesn’t Stop There! Introducing a RISC-V Webinar Series

This may not be as cool as a new chief executive - but it’s pretty darn close! On September 12, we will hold part one of a three-part (and our first ever) webinar series titled, “Getting Started with SiFive Coreplex IP”.

For part one - An Introduction to RISC-V for Embedded Developers - we will lay the groundwork and explain the basics of the RISC-V instruction set. This webinar is intended to give embedded developers a brief introduction into the RISC-V architecture. It assumes no prior RISC-V experience, so beginners welcome!

Want to learn more about the RISC-V ISA? Want a refresh on things you already know? 

Register Now!


All Aboard: A Weekly Update on RISC-V 

All Aboard logo (1).jpg

 That’s right - more new SiFive happenings to recap. Earlier this month, SiFive engineer Palmer Dabbelt launched a blog series called “All Aboard”, a weekly update on the RISC-V ecosystem. Check out the posts that have gone live thus far:


Upcoming Events


Were you unable to catch us at Hot Chips earlier this month? Didn’t get a chance to see Yunsup look at totality? No sweat! As Naveed mentioned, we will be all over the map at various industry conferences as 2017 winds to a close.

  • TSMC 2017 Open Innovation Forum, September 13, 2017
    • Drop by and say hello to us at booth 215, where we will be showing off our latest innovations and talking all things SiFive, RISC-V and open-source!
  • Linley Processor Conference, October 4-5, 2017
    • You will not want to miss this - Jack is set to debut the our newest Coreplex IP design, the U54 Coreplex. Register now!
  • International System-on-Chip Conference, October 18-19, 2017
    • The Linley Processor Conference isn’t the only event Jack will be speaking at in October. Make sure you catch him at the International SoC Conference held at UC Irvine!  
  • 7th RISC-V Workshop, November 28-30, 2017
    • The call for papers for the 7th RISC-V Workshop hosted by Western Digital in Milpitas, CA is live! Make sure to get your submissions in by the Sept. 17 deadline - hope to see you all there!
  • ESC Silicon Valley, December 5-7, 2017
    • At our second go around at ESC Silicon Valley, we will be taking a look at the growing RISC-V ecosystem, performance of open source-based embedded cores and solutions to the development challenges in using open source-based hardware for commercial projects.

Forum Highlight

There is lots going on over at the SiFive Forums, which you can access through the SiFive site. The forums are chalked full of valuable content that can answer your questions and curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that have our attention (and will now have yours, too!):


Featured Developer Of the Month

Our view of the world centers around the developer, the engineer, the user, the dreamer. It’s you who are contributing to RISC-V and open-source, making what we would do at SiFive possible.

This month’s feature developer is Mio Iwakura, better known as “Moitatsu” to his fans and followers. In addition to being an active member on the SiFive Forums, Mio has his own RISC-V YouTube series called “RISCY BUSINESS”, in which he has developed a handmade toolchain for RISC-V. Mio had Yunsup and Andrew on the series back in May - check it out!

We’d love to feature your SiFive project in the next newsletter - let us know what you are working on!


More Blog Posts

If you know us, you know that we are a chatty group. Here’s what has been on our minds (and our blog) over the past few months:

Our New Partnership with Rambus and the DesignShare Economy by Jack Kang

The FE310 is in a Museum – Which is Pretty Cool by Jack Kang

SiFive; The Journey to Becoming the Easiest Company to do Business With by Sander Arts

Employee Q&A: Introducing Renxin Xia by Staff


SiFive in the Press

Want to see who has been talking about SiFive recently? Let’s take a look!

SiFive Appoints Naveed Sherwani as CEO by Peter Clarke, eeNews Europe

Rambus Adds Security to RISC-V by Rick Merritt, EE Times

SiFive RISC-V and the Future of Computing! By Daniel Nenni, SemiWiki

Custom Processor Maker SiFive Appoints Intel Veteran as CEO by Dean Takahashi, VentureBeat


RISC-V in the News

We’re always keeping an eye on RISC-V; after all, our founders invented it! Check out the latest conversations around the RISC-V ISA:

Nvidia CEO Huang: Big Data, Self-Driven Cars, Gaming the ‘Big Vectors’ by Tiernan Ray, Barron’s
Look who Huang called an open-source company!

IP Challenges Ahead by Brian Bailey, SemiEngineering

Does RISC-V Mean Open Source Processors by Roddy Urquhart, Codasip

VexRiscv: A Modular RISC-V Implementation for FPGA by Al Williams, Hackaday

We would love to hear from you - reply to this email with any questions or inquiries and we will get right back to you!