The First RISC-V Webinar Was Great - Let’s do Another!

On Sept. 12, we held part one of our first-ever webinar series “An Introduction to RISC-V for Embedded Developers,” where we laid the groundwork and explained the basics of the RISC-V instruction set. Thank you to everyone who joined - we hope you all enjoyed it as much as we did!

On Oct. 17, we will host part two of the three-part RISC-V webinar series titled, “Introduction to SiFive IP,” which will explore the SiFive Coreplex IP products, E31 Coreplex and E51 Coreplex.

Weren’t able to join part I? Attended part I and looking to dive even deeper into the RISC-V ISA?

Eat, Drink, Connect - More to come from SiFive HQ

In coordination with the Linaro Connect conference held in San Francisco earlier this month, we had the pleasure of hosting a group of open-source developers at our new office in San Mateo! Those who made the trip were met with food and beverages, a short presentation from Yunsup and signed RISC-V books by the inventors themselves.

We would like to say a quick thank you to everyone that made it out! Looking forward to hosting more events in the very near future!

All Aboard: A Weekly Update on RISC-V 

In the last SiFive Download, we introduced Palmer Dabbelt’s blog series, “All Aboard,” a weekly update on the RISC-V ecosystem. Check out what Palmer has been up to since the last newsletter:

• All Aboard, Part 5: Per-march and per-mabi Library Paths on RISC-V systems
• All Aboard, Part 4: The RISC-V code models
• All Aboard, Part 3: Linker Relaxation in the RISC-V Toolchain

Upcoming Events

Did you miss us at the Linley Conference earlier this month? No sweat! Check out our slides from Jack’s presentation here.

• International System-on-Chip Conference, October 18-19, 2017
  • The Linley Processor Conference isn’t the only event Jack is speaking at in October. Make sure you catch him at the International SoC Conference held at UC Irvine!  
• 7th RISC-V Workshop, November 28-30, 2017
• The 7th RISC-V Workshop hosted by Western Digital in Milpitas, CA is just two months away! This is a must attend event for any and all who are interested in the RISC-V ISA - register here.
• ESC Silicon Valley, December 5-7, 2017
• At our second go around at ESC Silicon Valley, we will be taking a look at the growing RISC-V ecosystem, performance of open source-based embedded cores and solutions to the development challenges in using open source-based hardware for commercial projects. In addition, our very own Megan Wachs will be joining a “women in tech” panel!

Forum Highlight

There is lots going on over at the SiFive Forums, which you can access through the SiFive site. The forums are chalked full of valuable content that can answer your questions and curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that have our attention (and will now have yours, too!):

• LoFive RISC-V
• Is it possible to brick the HiFive board?
• SVD file for E310-G000

Featured Developer Of the Month

Our view of the world centers around the developer, the engineer, the user, the dreamer. It’s you who are contributing to RISC-V and open-source, making what we would do at SiFive possible.

One of the coolest things about what we do is seeing all the various implementations and iterations of RISC-V based projects. And (not to play favorites), but perhaps one of the coolest implementations we’ve seen came by the way of QWERTY Embedded Design’s Michael Welling and the LoFive board. The LoFive board has generated tremendous buzz in Twittersphere - and for good reason! This thing seriously rocks; check it out!

We’d love to feature your SiFive project in the next newsletter - let us know what you are working on!

More Blog Posts

If you know us, you know that we are a chatty group. Here’s what has been on our minds (and our blog) over the past few months:

Introducing the U54-MC Coreplex IP - The First RISC-V Core with Linux Support by Jack Kang  

RISC-V 101 Webinar by Jack Kang

SiFive; The Journey to Becoming the Easiest Company to do Business With by Sander Arts

Employee Q&A: Introducing Renxin Xia by Staff

SiFive in the Press

Want to see who has been talking about SiFive recently? Let’s take a look!

2018 Will be The Year of The RISC-V Linux Processors by Nick Farrell, Fudzilla

Linux Now Has its First Open Source RISC-V Processor by Chris Wiltz, Design News

SiFive Announces RISC-V SoC by Brian Benchoff, Hackaday

Hands-On HiFive RISC-V by Bill Wong, Electronic Design

Naveed Sherwani Takes Reins at SiFive by Paul McLellan, Cadence

SiFive’s Chief Executive on Opening a Chip Design Factory by James Morra, Electronic Design

RISC-V in the News

We’re always keeping an eye on RISC-V; after all, our founders invented it! Check out the latest conversations around the RISC-V ISA:

RISC-V Paper by Imperas at 15th International System-on-Chip (SoC) Conference 2017 by Staff, EE Journal

The Natural Evolution of Artificial Intelligence by Tiernan Ray, Barron’s

UltraSoC Expands After $6m Investment by Graham Pitcher, New Electronics

Roundtable: Experts Discuss Key Design Engineer Challenges by Staff, ECN Magazine

We would love to hear from you - reply to this email with any questions or inquiries and we will get right back to you!